Tomohiro Yokota, Shigeyoshi Watanabe, Analysis of pattern area reduction for logic circuit and system LSI with SGT

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CONTEMPORARY ENGINEERING SCIENCES

ISSN 1313-6569 (print) ISSN 1314-7641 (online)

Tomohiro Yokota, Shigeyoshi Watanabe
Analysis of pattern area reduction for logic circuit and system LSI with SGT
Contemporary Engineering Sciences, Vol. 8, 2015, no. 13, 589-601
http://dx.doi.org/10.12988/ces.2015.54134
Copyright © 2015 Tomohiro Yokota and Shigeyoshi Watanabe. This article is distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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