Tomohiro Yokota, Shigeyoshi Watanabe
      Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory
      Contemporary Engineering Sciences, Vol. 11, 2018, no. 20, 983-993
      https://doi.org/10.12988/ces.2018.8257

Copyright © 2018 Tomohiro Yokota and Shigeyoshi Watanabe. This article is distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.